VLSI circuit chips require a clocking scheme in order to execute instructions and transfer data across the many individual smaller circuit components. Ideally, clock signals would arrive at every circuit element within a VLSI circuit simultaneously. As a result, clock distribution networks in VLSI circuits have typically been designed such that the reference clock signal is distributed in a symmetric manner across the circuit from a centrally located clock reference. A balanced "H," a grid, a spine, and a tree are some examples of the physical layout of clock distribution networks across a VLSI chip.
Despite the symmetry associated with prior art clock distribution networks, imperfections in circuit conductors and clock signal repeaters, lead to random variations across the clock distribution network on a VLSI chip. These random variations introduced by flaws in manufacturing processes introduce clock skew. Clock skew is further affected by the different logic blocks implemented on a VLSI circuit. Since logic blocks perform different functions, it follows that each logic block is implemented with a different circuit stricture. Thus, during operation, the path taken in any given logic block varies from block to block. Different capacitive and resistive loads caused by the various logic elements also affect clock skew. In other words, different logic circuits and variations within the elements from logic block to logic block make it nearly impossible to match the rising and falling edges of different clocks across each individual logic block on a VLSI circuit.
Early generations of VLSI circuits used a single clock with a 50% duty cycle. Only a single operation could be performed during each individual clock cycle. As higher clock frequencies became not only desirable, but required, various schemes were employed to increase the allowable frequency of the clock cycle, for example, altering the duty cycle to increase the enable phase and to decrease the disable phase while maintaining the smallest possible clock period. A clear problem with this method was that the maximum allowable clock frequency was limited to the setup and hold time requirements of the individual physical components on the VLSI circuit. Other methods were needed to increase clock frequency.
One method for permitting greater clock frequency is known as "pipelining." In this method, a dual phase clock scheme is used by generating a differential pair of symmetric clocks in a centralized region of the VLSI circuit. In a simple "pipeline" configuration, logic for implementing operations is divided into specific "pipeline" stages, whereby each stage represents one clock cycle. Alternating stages receive the differential clock signals. Thus, while a given pipeline stage performs an operation during an enable phase, the subsequent pipeline stage, which depends on the output from the previous stage, waits during its disable cycle. As one of the differential clocks enters the disable cycle, the other differential clock enters the enable cycle, and the subsequent pipeline stage performs its designated operation.
Since typical pipelined clocking schemes generally use global clocks and a clock distribution network to apply the global clock to localized circuit blocks across the VLSI circuit, clock skew and the rise and fall times of the clocking signals received by each individual circuit blocks on a VLSI circuit are critical to circuit performance.
Clock skew reduces circuit performance by introducing race conditions and hold time problems. Race conditions occur when a first latch designed to maintain a data signal at a particular level for sampling by a circuit in a second clock zone on the VLSI circuit transitions prior to the sampling event. Race conditions introduce data transfer errors when the receiving circuit applies incorrect data. In a related manner, clock skew introduces hold time problems as clock signal delays at a data sending circuit reduce the time available for a data signal to reach a receiving circuit in a second clock zone. As a result of clock skew, the VLSI circuit can not be run as fast as intended. Clock skew is a function of load, clock network distribution across the dice and device mismatch, as well as, temperature and voltage gradients across the VLSI circuit.
Thus, a need exists in the industry to control clock skew between logic blocks across a VLSI circuit.